1. Field of the Invention
The present invention relates to a semiconductor package that includes a printed wiring board having a semiconductor element mounted thereon, and to a stacked semiconductor package having a package on package (PoP) structure.
2. Description of the Related Art
As one form of a semiconductor package, a stacked semiconductor package having a PoP structure is known (see Japanese Patent Application Laid-Open No. 2011-14757). This is a structure in which an upper semiconductor package (for example, a package having a DDR memory mounted thereon) is stacked on a lower semiconductor package (for example, a package having a system LSI mounted thereon).
The upper semiconductor package includes an upper semiconductor chip as a semiconductor element, and an upper printed wiring board having the upper semiconductor chip mounted thereon. The lower semiconductor package includes a lower semiconductor chip as a semiconductor element, and a lower printed wiring board having the lower semiconductor chip mounted thereon. Communication between the lower semiconductor chip and the upper semiconductor chip is made through transmission lines formed by solder joining lands of the lower printed wiring board and lands of the upper printed wiring board.
Generally, communication between semiconductor chips requires multiple transmission lines. As an example, when 8-bit communication is made between a system LSI and a DDR memory, eight bus wirings DQ[0] to DQ[7] for transmitting data signals and two differential signal wirings DQS and /DQS for transmitting strobe signals are necessary. In recent years, the system is more sophisticated in functionality, and the number of the transmission lines used for communication between the upper and lower semiconductor chips is far above 100.
Communication signals between semiconductor elements are required to be synchronized with each other to some extent so that malfunction does not occur. In order to ensure the synchronization, bus circuits or differential circuits provided in a semiconductor element are formed so as to have the same circuit characteristics. In addition, the bus wirings or the differential signal wirings as the transmission lines are required to have the same transmission line characteristics. In recent years, as the system becomes more sophisticated in functionality, signal speed is enhanced, and allowable synchronization becomes stricter.
However, the length of a wiring that extends from a signal terminal of the semiconductor element to a land varies depending on the position of the land, and thus, the length of the wiring varies, and, due to difference in parasitic inductance caused thereby, the transmission line characteristics vary. If the transmission line characteristics vary among wirings, in a semiconductor element on a signal receiving side, the waveform varies among multiple signals, and thus, it is difficult to ensure synchronization of the signals.